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| IX2R11 2A Half-Bridge Driver Features * Floating High Side Driver with boot-strap Power supply along with a Low Side Driver. * Fully operational to 650V * 50V/ns dV/dt immunity * Gate drive power supply range: 10 - 35V * Undervoltage lockout for both output drivers * Separate Logic power supply range: 3.3V to VCL * Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes * Latch-Up protected over entire operating range * High peak output current: 2A * Matched propagation delay for both outputs * Low output impedance * Low power supply current * Immune to negative voltage transients Preliminary Data Sheet General Description The IX2R11 Bridge Driver for N-channel MOSFETs and IGBTs with a high side and low side output, whose input signals reference the low side. The High Side driver can control a MOSFET or IGBT connected to a positive buss voltage up to 650V. The logic input stages are compatible with TTL or CMOS, have built-in hysteresis and are fully immune to latch up over the entire operating range. The IX2R11 can withstand dV/dt on the output side up to 50V/ns. The IX2R11 comes in either the 16-PIN SOIC package (IX2R11S3) or the 14-PIN DIP through-hole package (IX2R11P7) Applications * * * * * * Driving MOSFETs and IGBTs in half-bridge circuits High voltage, high side and low side drivers Motor Controls Switch Mode Power Supplies (SMPS) DC to DC Converters Class D Switching Amplifiers Warning: The IX2R11 is ESD sensitive. Figure 1. Typical Circuit Connection Power-Bus Voltage Copyright (c) IXYS CORPORATION 2004 IX2R11S3 DS99165A(08/04) First Release IX2R11 Figure 2 - IX2R11 Functional Block Diagram VDD VCH Low to HIN HIN DG High OUT RST IN UVCC Detect HS Isolated High Side VCL HS VCH HIN Gate Current Output HGO VDD VCL LIN Low to High Side Delay Equalizer and Shutdown Shutdown Logic UVCC Detect Gate Current Output LGO ENB DG DG 1 Ohm LS LS Pin Description And Configuration SYMBOL VDD HIN LIN ENB DG VCH HGO HS VCL LGO LS FUNCTION Logic Supply HS Input LS Input Not Enable Ground Supply Voltage Output Return Supply Voltage Output Ground 14-PIN DIP 8 DESCRIPTION Positive power supply for the chip CMOS functions High side Input signal, TTL or CMOS compatible; HGO in phase Low side Input signal, TTL or CMOS compatible; LGO in phase Chip enable. When driven high, both outputs go low. Logic Reference Ground High Side Power Supply High side driver output High side voltage return pin Low side power supply. This power supply provides power for both outputs. Voltage range is from 4.5 to 25V. Low side driver output Low side return 16-PIN SOIC HGO VCH 7 N/C VDD 9 6 11 ENB LIN DG NC N/C VCL LS LGO 4 12 3 13 2 14 1 2 IX2R11S3 10 IX2R11P7 HIN HS 5 IX2R11 Absolute Maximum Ratings Symbol VCH VHS VHGO VCL VLGO VDD VDG VIN dVS/dt PD PD RTHJA RTHJc TJ TS TL Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic supply voltage Logic supply offset voltage Logic input voltage(HIN & LIN) Allowable offset supply voltage transient Package power dissipation@ TA 25C Package power dissipation@ TC 25C Thermal resistance, junction-to-ambient Thermal resistance, junction-to-case Junction Temperature Storage temperature Lead temperature (soldering, 10 s) -55 Min -25 VCH-200 VHS-.3 -0.3 -0.3 -0.3 VLS-3.8 VSS-.3 Max 650 VCH+.3 VCH+.3 35 VCL+.3 VDG+35 VLS+3.8 VDD+.3 50 1.25 2.5 100 50 150 150 300 Units V V V V V V V V V/ns W W K/W K/W o o o C C C Recommended Operating Conditions Symbol VCH VHS VHGO VCL VLGO VDD VDG VIN TA Definition Min High side floating supply absolute voltage VHS+10 High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic supply voltage Logic supply voffset voltage Logic input voltage(HIN, LIN, ENbar) Ambient Temperature -20 VHS 10 0 VDG+3 VLS-1 VDG -40 Max VHS+20 650 VCH+20 20 VCC VDG+20 VLS+1 VDD 125 Units V V V V V V V V o C Ordering Information Part Number IX2R11P7 IX2R11S3 Package Type 14-PIN DIP 16-PIN SOIC 3 IX2R11 Dynamic Electrical Characteristics Symbol ton toff tenb tr tf tdm Symbol VINH VINL Definition Turn-on propagation delay Turn-off propagation delay Device Not enable delay Turn-on rise time Turn-off fall time Delay matching, HS & LS turn-on/off Cload= 2nF Cload= 2nF Cload= 2nF Test Conditions VDD= VCL= 15V VDD= VCC= 15V IO= 0A IO= 0A VHS= VCH= 600V VIN= 0V or VDD VIN= 0V or VDD VIN= 0V or VDD VIN= VDD VIN= 0V 0.28 .23 .17 .77 .79 36 2 1 8.3 8.2 8.1 8.0 A -2 A Min 7.0 6 Test Conditions VHS= 0V, Cload= 2nF VHS= 600V, Cload= 2nF Min Typ 120 87 202 23 22 10 20 Max Units ns ns ns ns ns ns Static Electrical Characteristics Definition Logic "1" input voltage Logic "0" input voltage VCH-VHGO or VCL-VLGO VLLGO // VLHGO High level output voltage, VHGO or VLGO IHL IQHS IQLS IQDD IIN+ IINVCHUV+ VCHUVVCLUV+ VCLUVIGO+ IGOHS to LS bias current. Quiescent VCH supply current Quiescent VCL supply current Quiescent VDD supply current Logic "1" input bias current Logic "0" input voltage mA mA mA uA uA uA V V V V V Typ Max Units V V V VHLGO // VHHGO High level output voltage, VCH supply undervoltage positive going threshold. VCH supply undervoltage negative going threshold. VCL supply undervoltage positive going threshold VCL supply undervoltage negative going threshold. HS or LS Output low short circuit current; VGO= 15V, VIN= 0V, PW<10us +2 HS or LS Output low short circuit current; VGO= 15V, VIN=0V, PW<10us Timing Waveform Definitions ENB HIN/LIN ENB 50% tenb LGO/HGO Figure 3. INPUT/OUPUT Timing Diagram 4 LGO/HGO 10% Figure 4. ENABLE Waveform Definitions IX2R11 Timing Waveform Definitions Figure 5. Definitions of Switching Time Waforms 50% HIN LIN tdon 90% HGO LGO tr 50% HIN LIN Figure 6. Definitions of Delay Matching Waveforms 50% 50% tdoff 90% Input Signal 90% LGO HGO 10% tdm tdm LGO HGO tf 10% 10% Outgoing Signal 15V U1 9 10 11 12 13 14 15 16 U2 15V 1 V1 18V Vin Vout 3 HS NC VDD HIN ENB LIN DG LS HGO VCH HS NC NC VCL LS LGO 8 7 6 5 4 3 2 1 + C2 10uF C5 0.1uF HGO HS OUTPUT MONITOR HV SCOPE PROBE IX2R11S3 GND2 L1 200uH + C3 10uF D1 DSEI12-10A GND2 100uF/250V + C1 C6 0.1uF GND1 dVs/dt > 50v/ns HV 600V GND GND1 15V V3 C8 0.1uF C9 10uF Q1 U2 2 1,8 6,7 IXDD414 4,5 -600V IXFP4N100Q GND3 D2 DSEI12-10A BATTERY 2 Measure dVdt ( HV Scope Probe ) BNC PULSE 2 U3 VCC 16 OUT 3 GND2 HCPL-314J 1/2 14 VEE 15 GND3 Figure 7. Test circuit for allowable offset supply voltage transient. 5 IX2R11 IX2R11S3 Package Outline IX6211P7 Package Outline IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: sales@ixys.net www.ixys.com IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: marcom@ixys.de 6 99165(04/04) |
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